Certain computing activities require a high precision clock that is distributed among a number of modules in a circuit, for example for high precision time stamping in a network device. High frequency clock signals offer suitable precision. However, the power cost of distributing a clock signal is related to its frequency.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.
SUMMARY
Systems and methods are provided for determining a clock time associated with an event at a higher precision than is attainable by a main clock signal. A system includes a plurality of processing modules distributed across an integrated circuit, a main clock signal being transmitted to ones of the plurality of processing modules at a main clock frequency. A plurality of sub-cycle frequency resolution modules are disposed in corresponding ones of the processing modules, the sub-cycle frequency modules generating sub-cycle phase indicators at a frequency that is greater than the main clock frequency, the sub-cycle frequency resolution modules being configured to receive the main clock signal and to determine a clock time of an event based on a combination of the main clock and the sub-cycle phase indicators. In an example, the processing modules are configured to time stamp data packets that are received and transmitted via a computer network.
As another example, a method for determining a clock time associated with an event at a higher precision than is attainable by a main clock signal of an integrated circuit includes transmitting a main clock signal having a main clock frequency to ones of a plurality of processing modules distributed across an integrated circuit. The sub-cycle frequency resolution modules are used to generate sub-cycle phase indicators at a frequency that is greater than the main clock frequency. A clock time of an event is determined at a higher precision than is attainable by the main clock signal at respective sub-cycle frequency resolution modules based on a combination of the main clock signal and the sub-cycle phase indicators.